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QUESTION NO: 32
Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?
A. A dedicated real-time clock to provide the total cycle count
B. Use of the divide-by 64 counting option to avoid an overflow of the cycle counter
C. Use of the overflow interrupts, to extend the range of the built-in 32-bit counter
D. Modification of the application software being profiled, to insert timestamps at regular intervals
Answer: C
QUESTION NO: 33
Which of the following is preserved in dormant mode?
A. Core register contents
B. CP15 (system) register settings
C. Debug state
D. Cache contents
Answer: D
QUESTION NO: 34
In general, when programming in C, stack accesses will be reduced by:
A. Disabling inlining.
B. Never passing more than four parameters in function calls.
C. Declaring automatic variables as “packed”.
D. Configuring the compiler to optimize for space.
Answer: B
QUESTION NO: 35
Consider the following instruction sequence:
STR r0, [r2] ; instruction A
DSB
ADD r0, r1, r2 ; instruction B
LDR r3, [r4] ; instruction C
SUB r5, r6, #3 ; instruction D
At what point will execution pause until the STR access is complete?
A. After instruction A and before the DSB
B. After the DSB and before instruction B
C. After instruction B and before instruction C
D. After instruction C and before instruction D
Answer: B
QUESTION NO: 36
What is an “Entry point” in an application?
A. A place where execution can start
B. The location of the main () function
C. The lowest address contained in a program image
D. A location where the linker can store additional information
Answer: A QUESTION NO: 37
In an ARMv7-A processor, with which level of the memory system is the Memory Management Unit (MMU) associated?
A. Level 1
B. Level 2
C. Level 3
D. Level 4
Answer: A
QUESTION NO: 38
An application contains three calls to an external function, foobar(), which is defined in a shared (or dynamic) library. How many copies of foobar() will the linker place in the application image?
(Ignore linker inlining)
A. None
B. Always one
C. Always three
D. One or more depending on optimization level
Answer: A
QUESTION NO: 39
In an MPCore system, when one core is waiting for resources to be released, what instruction could be used to reduce that core’s power consumption?
A. WFE
B. PLD
C. NOP
D. DSB
Answer: A
QUESTION NO: 40
According to the AAPCS (with soft floating point linkage), when the caller “func” calls sprintf, where is the value of the parameter “x” placed?
#include <stdio.h>
void func(double x, int i , char *buffer)
{
sprintf(buffer, “pass %d: value = %f\n”, i, x); }
A. Split between register R3 and 4 bytes on the stack
B. Split between registers R3 and R4
C. 8 bytes on the stack
D. VFP Register D0
Answer: C
QUESTION NO: 41
In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!
A. 0x80003FF8
B. 0x80004000
C. 0x80004008
D. R1 contents are unpredictable
Answer: B
QUESTION NO: 42
Which of the following operations would count as intrusive to normal processor operation?
A. Tracing using Embedded Trace Macrocell (ETM)
B. Halt mode debugging
C. Monitor mode debugging
D. Using the Performance Monitor Unit
Answer: B
QUESTION NO: 43
In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?
A. In system memory
B. In registers shared with the VFP register set
C. In registers shared with the integer register set
D. In dedicated registers not shared with other registers
Answer: B
QUESTION NO: 44
Which of the following sequences of stages comprise the ARM7TDMI three-stage pipeline?
A. Fetch, Decode, Execute
B. Decode, Fetch, Execute
C. Execute, Fetch, Decode
D. Fetch, Execute, Execute
Answer: A QUESTION NO: 45
According to the AAPCS, which of the following statements is TRUE with regard to preservation of register values by a function?
A. A function must preserve R0-R3 and R12
B. A function must preserve R4-R11 andR13
C. No registers may be corrupted by any function
D. All registers may be corrupted by any function
Answer: B
QUESTION NO: 46
An advantage of native compiling over cross compiling is that:
A. It can enable the final code to be smaller, and execute more quickly.
B. It allows greater parallelism when building code by utilizing many processors.
C. The compiler is able to produce error and warning messages in a range of languages.
D. Build scripts can detect details of the target, and automatically configure the build to match.
Answer: D
QUESTION NO: 47
An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.
STR r0, [r1] ; write to interrupt controller register to clear interrupt request
<x>
CPSIE i ; re-enable IRQ interrupts Which of the following instructions should be placed at position <x> in order to ensure that the interrupt controller sees the write before interrupts are re-enabled?
A. DMB
B. DSB
C. ISB
D. NOP
Answer: B
QUESTION NO: 48
The purpose of a translation lookaside buffer (TLB) is to:
A. Protect memory.
B. Improve performance.
C. Implement virtual memory,
D. Ensure correct ordering of memory operations.
Answer: B
QUESTION NO: 49
How many bytes of stack are needed to pass parameters when calling the following function?
int foo( short arg_a, long long arg_b, char arg_c, int arg_d )
A. 0
B. 4
C. 8
D. 15
Answer: C
QUESTION NO: 50
Which one of the following statements is TRUE for software breakpoints?
A. Limited software breakpoints can be placed in code running from ROM
B. Each software breakpoint requires one watchpoint resource in the debug hardware
C. Each software breakpoint requires one breakpoint resource in the debug hardware
D. The number of available software breakpoints is not limited by the debug hardware
Answer: D
QUESTION NO: 51
Using a lower optimization level when compiling will:
A. Produce faster code.
B. Produce smaller code.
C. Produce non standard-compliant code.
D. Produce code that might be easier to debug.
Answer: D
QUESTION NO: 52
Which instruction would be used to return from a Reset exception?
A. MOVS PC, R14
B. MOVSPC, R13
C. Architecturally not defined
D. SUBS PC, R14, #4
Answer: C
QUESTION NO: 53
In a Cortex-A9 MPCore cluster with four processors, which of the processors can be interrupted by a software-generated interrupt?
A. Any processor in the cluster
B. Only the processor raising the software-generated interrupt
C. Only processors outside the cluster
D. Any processor except the one raising the software-generated interrupt
Answer: A
QUESTION NO: 54
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
A. PC=LR
B. PC=LR44
C. PC=LR-4
D. PC=LR-8
Answer: D
QUESTION NO: 55
Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?
A. R0=0x100, R1 =0x1000
B. R0=0x100, R1=0x1002
C. R0=0x101, R1=0x1002
D. R0=0x101. R1=0x1003
Answer: D
QUESTION NO: 56
Which ARMv7 instructions are recommended to implement a semaphore?
A. SWP, SWPB
B. TEQ, TST
C. STC, SBC
D. LDREX, STREX
Answer: D
QUESTION NO: 57
Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?
A. Cache support
B. Privileged execution
C. The ARM instruction set
D. Virtual memory support
Answer: D
QUESTION NO: 58
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
A. 0
B. 4
C. 8
D. 12
Answer: A QUESTION NO: 59
The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:
data = 123;
ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
A. DSBSY
B. DSBST
C. DMBSY
D. DMBST
Answer: D
QUESTION NO: 60
On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?
A. This transition is not possible
B. Execution of an SMC instruction
C. Execution of an SMC instruction followed by an SVC instruction
D. Execution of an SVC instruction followed by an SMC instruction
Answer: D
QUESTION NO: 61
What architecture does the ARM11 MPCore implement?
A. ARMv6
B. ARMv6K
C. ARMv7-A
D. ARMv7-A with the Multiprocessing Extensions
Answer: B
QUESTION NO: 62
The following function is declared: float func(float fl, float f2);
The file file1 .c contains a call to func, and is compiled with hard floating point linkage. The file file2.c contains the definition of func, and is compiled with AACPS soft floating point linkage.
Assume that the two files are successfully linked using the ARM linker and an executable is generated. The generated executable:
A. Exhibits correct behavior, but suffers a performance penalty because the linker has to generate extra code.
B. Exhibits correct behavior, and suffers no performance penalty.
C. Will not execute.
D. Exhibits incorrect behavior.
Answer: D
QUESTION NO: 63
During an investigation into a software performance problem an engineer doubles the clock frequency of a cached ARM processor running the software. Unfortunately the performance of the application does not increase by very much, despite running on the processor for 100% of the time. What is likely to be the main bottleneck in the system?
A. The processor is context switching between multiple processes
B. Performance is limited by the speed of external memory
C. The processor is taking too long to execute branch instructions
D. The system is raising interrupts too fast for the processor to handle them
Answer: B QUESTION NO: 64
In which of the following situations would you use a mutex to avoid synchronization problems?
A. A single-threaded application needs to manage two separate UART peripherals
B. Two independent threads running on a single processor both need to access a single UART
C. In a dual-core system, a UART is accessed by a single thread running on one of the processors
D. In a dual-core system, processor A needs to access UART A and processor B needs to access UART B
Answer: B
QUESTION NO: 65
Which of the following will cause the ARM Compiler to target the Thumb instruction set?
A. Compiling exception handlers
B. Specifying a Thumb-capable processor (e.g. -cpu=Cortex-A9)
C. Enabling Thumb code generation on the command line (–thumb)
D. Configuring the compiler for maximum code density (-Ospace)
Answer: C
QUESTION NO: 66
Which TWO of the following options can the ARM Compiler (armcc) directive__packed be used for? (Choose two)
A. To tell the compiler to use only Thumb code
B. To tell the compiler to produce code of minimum size
C. To tell the compiler to use the v6 SIMD pack/unpack instructions
D. To tell the compiler that an object can be on an unaligned address
E. To tell the compiler not to perform padding inside structures
Answer: D,E
QUESTION NO: 67
When using an Operating System, which of the following operations can NOT typically be done by user processes?
A. Reading the link register (R14)
B. Reading data from the user stack
C. Changing from ARM state to Thumb state
D. Changing the interrupt mask bits (A, I, F) in the CPSR
Answer: D
QUESTION NO: 68
In the ARM instruction set what is the maximum branch distance for a Branch or Branch and Link instruction?
A. ±32MB
B. ±4MB
C. ±12KB
D. ±4KB
Answer: A
QUESTION NO: 69
Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?
A. Cortex-M0+
B. Cortex-M4
C. Cortex-R4
D. Cortex-A15
Answer: A QUESTION NO: 70
In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a Non-secure privileged mode?
A. The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory
B. Secure memory contents are encrypted, and cannot be decrypted by Non-secure software
C. The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set
D. The MMU generates an abort on accesses to Secure memory performed by Non-secure software
Answer: A
QUESTION NO: 71
Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)
A. Unaligned accesses may take more cycles to execute than aligned accesses
B. Unaligned loads and stores are necessary for accessing fields in packed structures
C. A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices
D. If the relevant control register setting is enabled all loads and stores can function from unaligned addresses
E. Unaligned accesses can only be made to Normal memory
Answer: A,E
QUESTION NO: 72
The Cortex-A9 MPCore processor contains a hardware block whose function is to maintain data cache coherency between cores. What is the name of this block?
A. Shareable Memory
B. Snoop Control Unit
C. Private Memory Region
D. Level 2 Cache Controller
Answer: B
QUESTION NO: 73
Which TWO of the following accurately describe constraints on the location of the Tightly Coupled Memory (TCM) regions in a Cortex-R4 processor? (Choose two)
A. TCM Region A (ATCM) must be at a lower memory address than TCM Region B (BTCM)
B. TCM Region A can only be located at address 0x0
C. Both TCM regions must be placed at addresses which are aligned to their size
D. The two TCM regions may not overlap
E. TCM Region B (BTCM) must be located immediately above TCM Region A (ATCM)
Answer: C
QUESTION NO: 74
Which of the following processor resources do NOT have to be saved or modified by the Linux scheduler during context switch?
A. Registers R0-R15
B. Thread and process ID registers
C. The CPSR
D. NEON and VFP registers
Answer: D QUESTION NO: 75
A function written in C has the prototype:
void my_function(float a. double b, float c);
The function is built and linked into an application using hard floating-point linkage. What registers are used to pass arguments to the function?
A. a->s0; b->d0; c->s1
B. a->s0; b->d1; c->s1
C. a->d0; b->d1; c->d2
D. a->s0; b->d1; c-> s2
Answer: B
QUESTION NO: 76
Under which of the following circumstances is TLB maintenance always required?
A. If a TLB miss occurs
B. On every process switch
C. If the TLB reports a fault
D. When a page table entry is changed
Answer: D
QUESTION NO: 77
Which one of the following debug methods is the least intrusive for analyzing a timing related bug?
A. Place breakpoints on strategic locations to locate the problem area
B. Instrument the code with print statements to locate the problem area
C. Use debug hardware to place watchpoints on strategic data memory locations
D. Use trace hardware to capture a trace log up to the point of the crash
Answer: D QUESTION NO: 78
In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)
A. Processor reset
B. Switching from ARM to Thumb state
C. Changing the access permissions of a page
D. Executing a Data Memory Barrier instruction
E. Loading data from an unaligned memory address
Answer: A,C
QUESTION NO: 79
The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.
In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?
A. WFENE at <A>, SEV at <C>
B. WFEEQ at <A> SEV at <D>
C. WFE at<B> SEV at<C> WFENE at <B>
D. SEV at<D>
Answer: B
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